14th International Symposium on Mathematical Programming

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THE FIRST GENERATION 47 The chip count of the PPN filterbank stands at around 25. Lm double-metal CMOS, would consist of only 3 chips [148]. Lm nMOS. The technoLogicaL inflexibility of FIRST prevents advances in integration. Although the best available mixture of FIR and FFT architectures was chosen (obviating memory interfaces), some inefficiency had to be accepted in the FIR filterbank. This subsystem could have been implemented in 8-bit arithmetic, however the FFT demanded 16-bit precision. Thus the filterbank was required to idle on sign-extensions for 50% of the time, compromising the elegance of the overall system architecture.

We say 2 pairs (rather than 4) because we may take advantage of the fact that samples are 'bounced' between filter pairs (the subsampling ratio is 32 and there are 64 filters), and storage may be shared. 7 illustrates this. 7: sample-bouncing filter pair The signal memory is simple first-in-first-out (FIFO), but the coefficient memory must include the ability to recirculate M samples once they have been read. It therefore consists of a memory loop containing a multiplexer under control of an event pulse of length M words.

As the FFT is the more difficult to design, the multiplexing scheme appropriate to the FFT may also be used in the filterbank. 1. Lm nMOS function library (maximum 8 MHz clock rate) could be relaxed within reason for the purposes of this study. The overall latency of the implementation is not of concern, which allows some extra design freedom. System outputs are in rectangular (real/imaginary) form. INITIAL DESIGN ISSUES AND DECISIONS The PPN filterbank consists mainly of a bank of short transversal filters whose outputs form the inputs to an FFT subsystem.

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